IPC Manuals & Standards

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    J-STD-005

    Lists requirements for qualification and characterization of solder paste.

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    Test methods and criteria for metal content, viscosity, slump, solder ball, tack and wetting of solder pastes are included. Developed by IPC and EIA.

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    J-STD-006

    This standard prescribes the nomenclature, requirements and test methods for electronic grade solder alloys; for fluxed and non-fluxed bar, ribbon and powder solders for electronic soldering applications; and for ‘‘special’’ electronic grade solders.

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    This is a quality control standard and is not intended to relate directly to the material’s performance in the manufacturing process. Solders for applications other than electronics should be procured using ASTM B-32. This standard is one of a set of three joint industry standards that prescribe the requirements and test methods for soldering materials to be used in the electronics industry. The other two standards in this set are IPC/EIA J-STD-004, Requirements for Soldering Fluxes, and IPC/EIA J-STD-005, Requirements for Soldering Pastes. 29 pages. Released October 2009.Amendments 1 and 2 included in this J-STD-006 modify the following:

    • Add reference to IPC/JEDEC J-STD-609, Lead-Free and Leaded Marking,Symbols and Labels
    • Clarify the meaning of those alloys that are designated as lead-free
    • Provide guidance to suppliers how to designate and mark lead-free alloys
    • Correct the required maximum levels of lead (Pb) and antimony (Sb) allowed as impurities in section 3.3 Alloy Impurities
    • Transfer all information references on solder powder particle size distribution and solder paste products to IPC J-STD-005, Requirements for Solder Pastes
    • Remove Table 3-1 “Particle Size Distributions of Standard Solder Powders”
    • Change the information contained in Table A-1 “Composition and Temperature Characteristics of Lead-free Solder 8. Alloys” (contained in Appendix A “Solder Alloys”) and
    • Establish a consistent maximum contaminant level requirement within Appendix B-1 for the elements of silver (Ag), lead (Pb) and antimony (Sb)

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    J-STD-020

    Updated with extended support for components used for lead free assembly!

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    This standard identifies the classification levels of nonhermetic solid state surface mount devices that are sensitive to moisture-induced stress. It is used to determine which classification level should be used for initial reliability qualification. These devices can be properly packaged, stored, and handled to avoid subsequent thermal/mechanical damage during solder reflow attachment. Developed by IPC and JEDEC.

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    J-STD-026

    This standard addresses semiconductor flip chip design requirements.

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    Provides information for using standard semiconductor substrates, materials, assembly and test methods with established fabrication, bumping, test and handling practices. Electrical, thermal and mechanical chip design parameters and methodologies are covered in the standard, as well as the reliability aspects associated with these conditions and processes. The information applies to all new designs as well as modifications of non-flip chip designs. Developed by IPC and EIA.

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    J-STD-027

    This standard establishes mechanical outline requirements for devices supplied in flip chip or Chip Size Package (CSP) formats, including die surface, die terminals, and interconnection balls/bumps/lands to the next level.

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    J-STD-033

    Provides Surface Mount Device manufacturers and users with standardized methods for handling, packing, shipping and use of moisture/reflow sensitive SMDs.

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    These methods help avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. By using these procedures, safe and damage-free reflow can be achieved with the dry packing process, providing a minimum shelf life of 12 months from the seal date when using sealed dry bags. Developed by IPC and JEDEC.

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    £65.00 Enquiry Form
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    J-STD-035

    This test method defines the procedures for performing acoustic microscopy on non-hermetic encapsulated electronic components.

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    It provides users with an acoustic microscopy process flow for detecting defects non-destructively in plastic packages while achieving reproducibility. Developed by IPC and JEDEC.

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    J-STD-32

    This standard, developed jointly by IPC and the Electronic Industries Association (EIA) establishes the construction detail requirements for balls and other terminal structures on Ball Grid Array (BGA) packages.

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    It also establishes a set of designations and expectations for product performance. A large variety of terminal structures are recognized for a wide range of applications ranging from highest reliability computer, space and military applications to disposable commodity applications. 10 pages. Released June 2002.

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    J-STD-609

    This standard provides a marking and labeling system that aids in assembly, rework, repair and recycling.

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    This standard also provides for the identification of:1) those assemblies that are assembled with lead-containing or lead-free solder;
    2) components that have lead-containing or lead-free second level interconnect terminal finishes and materials;
    3) the maximum component temperature not to be exceeded during assembly or rework processing;
    4) the base materials used in the PCB construction, including those PCBs that use halogen-free resin;
    5) the surface finish of PCBs; and
    6) the conformal coating on PCBAs.
    New to this revision are additional codes for the more precise specification of certain lead-free solders. 13 pages. Released February 2010.

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